1. Technical Field
This invention relates to semiconductor memory devices, and more particularly, to the input/output pad configuration, or “layout,” on a semiconductor memory die.
2. Related Art
In one known type of a semiconductor memory package, a semiconductor memory die, or “chip,” is mounted on the die paddle of a metal lead frame, and includes a number of input/output wire bonding pads, each coupled to a metallization layer via a bond wire. The die and a portion of the metallization layer are encapsulated in plastic, ceramic or other material. The metallization layer is then cut apart or otherwise processed to free the individual leads, which extend from the package and are used to connect the package to other circuitry.
Many semiconductor devices, such as static random access memories (SRAMs), dynamic random access memories (DRAMs), and first-in first-out devices (FIFOs), include memory arrays. These memory arrays are formed by memory cells arranged in arrays of rows and columns. Thus, the layout of the pads on the die determines the length of conductive traces between those pads and the memory arrays.
The length of the data bus coupled to a memory array is related to the delay over that bus. For example, resistance-capacitance (RC) delay increases as the length of the bus increases. Correspondingly, RC delay on a semiconductor die between a memory array and a pad increases as the length of a conductive trace between the memory array and the pad increases. Thus, there is a need to minimize the length of the conductive traces between the memory arrays and the corresponding pads on the die.
Some memory devices may be adapted to operate in more than one configuration or mode. For example, in one mode, a memory device may be adapted to accommodate data words of a first width and in a second mode, the memory device may be adapted to accommodate data words of a second width, where the second width is greater than the first width. Typically, however, when the chip operates in one mode, the chip requires a first pin sequence and when the chip operates in second mode, the chip requires a second pin sequence different from the first pin sequence. Conventionally, providing a chip with pads for connecting to more than one pin sequence has required the elongation of an internal data bus to provide connection to pads adjacent associated pins to accommodate the second pin sequence. As discussed above, RC delay on a semiconductor die between a memory array and a pad increases as the length of a conductive trace, or bus, between the memory array and the pad increases.